Replacement conductive hard mask for multi-step magnetic tunnel junction (mtj) etch

ABSTRACT

A multi-step etch technique for fabricating a magnetic tunnel junction (MTJ) apparatus includes forming a first conductive hard mask on a first electrode of the MTJ apparatus for etching the first electrode during a first etching step. The method also includes forming a second conductive hard mask on the first conductive hard mask for etching magnetic layers of the MTJ apparatus during a second etching step. A spacer layer is conformally deposited on sidewalls of the first conductive hard mask. The second conductive hard mask is deposited on the first conductive hard mask and aligned with the spacer layer on the sidewalls of the first conductive hard mask.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. patent application Ser. No.14/243,324, entitled “REPLACEMENT CONDUCTIVE HARD MASK FOR MULTI-STEPMAGNETIC TUNNEL JUNCTION (MTJ) ETCH,” filed on Apr. 2, 2014, thedisclosure of which is expressly incorporated by reference herein in itsentirety.

TECHNICAL FIELD

The present disclosure generally relates to magnetic tunnel junction(MTJ) devices. More specifically, the present disclosure relates tofabricating high density arrays of magnetic random access memory (MRAM)devices.

BACKGROUND

Unlike conventional random access memory (RAM) chip technologies, inmagnetic RAM (MRAM) data is stored by magnetization of storage elements.The basic structure of the storage elements consists of metallicferromagnetic layers separated by a thin tunneling barrier. Typically,the ferromagnetic layers underneath the barrier (e.g., the pinned layer)have a magnetization that is fixed in a particular direction. Theferromagnetic magnetic layers above the tunneling barrier (e.g., thefree layer) have a magnetization direction that may be altered torepresent either a “1” or a “0.” For example, a “1” may be representedwhen the free layer magnetization is anti-parallel to the fixed layermagnetization. In addition, a “0” may be represented when the free layermagnetization is parallel to the fixed layer magnetization or viceversa. One such device having a fixed layer, a tunneling layer, and afree layer is a magnetic tunnel junction (MTJ). The electricalresistance of an MTJ depends on whether the free layer magnetization andfixed layer magnetization are parallel or anti-parallel to each other. Amemory device such as MRAM is built from an array of individuallyaddressable MTJs.

To write data in a conventional MRAM, a write current, which exceeds acritical switching current, is applied through an MTJ. Application of awrite current that exceeds the critical switching current changes themagnetization direction of the free layer. When the write current flowsin a first direction, the MTJ may be placed into or remain in a firststate in which its free layer magnetization direction and fixed layermagnetization direction are aligned in a parallel orientation. When thewrite current flows in a second direction, opposite to the firstdirection, the MTJ may be placed into or remain in a second state inwhich its free layer magnetization and fixed layer magnetization are inan anti-parallel orientation.

To read data in a conventional MRAM, a read current may flow through theMTJ via the same current path used to write data in the MTJ. If themagnetizations of the MTJ's free layer and fixed layer are orientedparallel to each other, the MTJ presents a parallel resistance. Theparallel resistance is different than a resistance (anti-parallel) theMTJ would present if the magnetizations of the free layer and the fixedlayer were in an anti-parallel orientation. In a conventional MRAM, twodistinct states are defined by these two different resistances of an MTJin a bitcell of the MRAM. The two different resistances indicate whethera logic “0” or a logic “1” value is stored by the MTJ.

MRAM is a non-volatile memory technology that uses magnetic elements.For example, spin transfer torque magnetoresistive random access memory(STT-MRAM) uses electrons that become spin-polarized as the electronspass through a thin film (spin filter). STT-MRAM is also known as spintransfer torque RAM (STT-RAM), spin torque transfer magnetizationswitching RAM (Spin-RAM), and spin momentum transfer (SMT-RAM).

Bitcells of a magnetic random access memory may be arranged in one ormore arrays including a pattern of memory elements (e.g., MTJs in caseof MRAM). Spin-transfer-torque magnetic random access memory (STT-MRAM)is an emerging nonvolatile memory that has advantages of non-volatility.In particular, STT-MRAM operates at a higher speed than off chip dynamicrandom access memory (DRAM). In addition, STT-MRAM has a smaller chipsize than embedded static random access memory (eSRAM), unlimitedread/write endurance, and a low array leakage current.

SUMMARY

A method of fabricating a magnetic tunnel junction (MTJ) apparatusaccording to an aspect of the present disclosure includes conformallydepositing a first spacer layer on a first conductive hard mask, on afirst electrode layer, and on magnetic layers of the MTJ. A firstportion of the first spacer layer is deposited on sidewalls of the firstconductive hard mask and a second portion of the spacer layer isdeposited on a surface of the first conductive hard mask. The methodalso includes selectively removing the second portion of the firstspacer layer to create a recess within a dielectric layer, which isaligned with the first portion of the first spacer layer. According tothis aspect of the present disclosure, the method also includes fillingthe recess with a conductive material to form a second conductive hardmask on the first portion of the first spacer layer and on the firstconductive hard mask.

An MTJ apparatus according to an aspect of the present disclosureincludes a first conductive hard mask on a second electrode layer. Thesecond electrode layer is on a stack of MTJ layers and is electricallycoupled to the stack of MTJ layers. The MTJ apparatus includes a firstspacer on sidewalls of the first conductive hard mask, sidewalls of thesecond electrode layer, and a surface of the stack of MTJ layers.According to this aspect of the present disclosure, the MTJ apparatusalso includes a second conductive hard mask aligned with sidewalls ofthe first spacer. The second conductive hard mask is on the firstconductive hard mask and on the first spacer.

An MTJ apparatus according to another aspect of the present disclosureincludes first means for masking a first electrode layer that is coupledto a stack of MTJ layers and for providing a conductive path to thefirst electrode layer. The first masking means abuts the first electrodelayer. The MTJ apparatus also includes means for protecting sidewalls ofthe first means. The protecting means abuts the sidewalls of the firstmeans, sidewalls of the first electrode layer, and a surface of thestack of MTJ layers. According to this aspect of the present disclosure,the MTJ apparatus also includes second means for masking the stack ofMTJ magnetic layers and for electrically coupling to the firstconductive path. The second means are aligned with sidewalls of thefirst means and abuts a surface of the first means.

This has outlined, rather broadly, the features and technical advantagesof the present disclosure in order that the detailed description thatfollows may be better understood. Additional features and advantages ofthe disclosure will be described below. It should be appreciated bythose skilled in the art that this disclosure may be readily utilized asa basis for modifying or designing other structures for carrying out thesame purposes of the present disclosure. It should also be realized bythose skilled in the art that such equivalent constructions do notdepart from the teachings of the disclosure as set forth in the appendedclaims. The novel features, which are believed to be characteristic ofthe disclosure, both as to its organization and method of operation,together with further objects and advantages, will be better understoodfrom the following description when considered in connection with theaccompanying figures. It is to be expressly understood, however, thateach of the figures is provided for the purpose of illustration anddescription only and is not intended as a definition of the limits ofthe present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present disclosure, referenceis now made to the following description taken in conjunction with theaccompanying drawings.

FIG. 1 is a diagram of a magnetic tunnel junction (MTJ) device connectedto an access transistor.

FIG. 2 is a conceptual diagram of a conventional magnetic random accessmemory (MRAM) cell including an MTJ.

FIG. 3 is a schematic cross-sectional view of a conventional MTJ stack,illustrating portions of the MTJ stack susceptible to process relateddamage.

FIGS. 4A-4B are schematic cross-sectional views of a partiallyfabricated MTJ structure illustrating a currently known two-step etchingtechnique for protecting the MTJ stack from process related damage.

FIGS. 5A-5J are schematic cross-sectional views of an MTJ structureduring fabrication according to aspects of the present disclosure.

FIG. 6 is a process flow diagram illustrating an exemplary method ofconstructing an MTJ structure according to aspects of the presentdisclosure.

FIG. 7 is a block diagram showing an exemplary wireless communicationsystem in which a configuration of the disclosure may be advantageouslyemployed.

FIG. 8 is a block diagram illustrating a design workstation used forcircuit, layout, and logic design of a semiconductor component accordingto one configuration.

DETAILED DESCRIPTION

The detailed description set forth below, in connection with theappended drawings, is intended as a description of variousconfigurations and is not intended to represent the only configurationsin which the concepts described herein may be practiced. The detaileddescription includes specific details for the purpose of providing athorough understanding of the various concepts. It will be apparent,however, to those skilled in the art that these concepts may bepracticed without these specific details. In some instances, well-knownstructures and components are shown in block diagram form in order toavoid obscuring such concepts. As described herein, the use of the term“and/or” is intended to represent an “inclusive OR”, and the use of theterm “or” is intended to represent an “exclusive OR”.

A memory device such as MRAM is built from an array of individuallyaddressable magnetic tunnel junction (MTJs). An MTJ stack may include afree layer, a fixed layer and a tunnel barrier layer there between aswell as one or more ferromagnetic layers. The MTJ stack is susceptibleto damage during the etching process due to re-deposition of etchingbyproducts. For example, removal of photoresist may include processessuch as oxygen ashing. Oxygen ashing can cause damage to the hard masklayer (e.g., an electrode layer) during the photoresist removal process.Oxygen ashing can also cause damage to upper portions of the sidewallsof the free layer of the MTJ stack. An etching process proceeds frometching the hard mask layer of the MTJ stack 300 to etching the fixedlayers (e.g., pinned) of the stack. As the etching process progressesthrough the MTJ stack, damage can be caused to the sidewalls 322 of thefree layer 314. As the etching process proceeds further, upper portionsand lower portions of the sidewalls of the tunneling barrier layer mayalso be damaged.

Non-volatile byproducts of the etching process may also settle asre-deposited films around the sidewalls of the MTJs of a memory device.The re-deposited films may act as leakage paths along the sidewalls,thereby reducing the magnetic resistance (MR) ratio of the MTJ. Suchprocess related damages may result in significantly lower yields.Existing techniques do not provide an effective solution for protectingMTJs from at least all these process related damages.

A method of implementing a two-step MTJ etching process according to anaspect of the present disclosure is described. In this aspect of thedisclosure, a spacer is protected during a second etching step.

FIG. 1 illustrates a memory cell 100 including a magnetic tunneljunction (MTJ) 102 coupled to an access transistor 104. A free layer 110of the MTJ 102 is coupled to a bit line 112. The access transistor 104is coupled between a fixed layer 106 of the MTJ 102 and a fixedpotential node 122. A tunnel barrier layer 114 is coupled between thefixed layer 106 and the free layer 110. The access transistor 104includes a gate 116 coupled to a word line 118.

Synthetic anti-ferromagnetic materials may be used to form the fixedlayer 106 and the free layer 110. For example, the fixed layer 106 maycomprise multiple material layers including a cobalt-iron-boron (CoFeB)layer, a ruthenium (Ru) layer and a cobalt-iron (CoFe) layer. Inaddition, the free layer 110 may be an anti-ferromagnetic material, suchas CoFeB, and the tunnel barrier layer 114 may be magnesium oxide (MgO).

FIG. 2 illustrates a conventional STT-MRAM bit cell 200. The STT-MRAMbit cell 200 includes a magnetic tunnel junction (MTJ) storage element205, a transistor 201, a bit line 202 and a word line 203. The MTJstorage element is formed, for example, from at least two ferromagneticlayers (a pinned layer and a free layer), each of which can hold amagnetic field or polarization, separated by a thin non-magneticinsulating layer (tunneling barrier). Electrons from the twoferromagnetic layers can penetrate through the tunneling barrier due toa tunneling effect under a bias voltage applied to the ferromagneticlayers. The magnetic polarization of the free layer can be reversed sothat the polarity of the pinned layer and the free layer are eithersubstantially aligned or opposite. The resistance of the electrical paththrough the MTJ varies depending on the alignment of the polarizationsof the pinned and free layers. This variance in resistance may be usedto program and read the bit cell 200. The STT-MRAM bit cell 200 alsoincludes a source line 204, a sense amplifier 208, read/write circuitry206 and a bit line reference 207.

As shown in FIG. 3, conventional MTJ storage elements generally areformed on an electrode 302 (e.g., a bottom electrode) such as asemiconductor substrate (e.g., of Si). One or more seed layers (notshown) may be formed on the electrode 302. Generally, anantiferromagnetic (AFM) layer 304 is first formed on the electrode 302,and then a first ferromagnetic layer is formed on of the AFM layer 304.The first ferromagnetic layer is “pinned” with a fixed magnetization toform a pinned layer. The pinned layer may include one or more layers,such as a first pinned layer 306 (e.g., a bottom pinned layer), acoupling layer 308 typically formed of a non-magnetic metal such asruthenium (Ru), and a second pinned layer 310 (e.g., a top pinnedlayer). A tunneling barrier layer 312, including an insulator (e.g., ametal oxide), is formed on the second pinned layer 310. A free layer 314of a second ferromagnetic layer is formed directly on the tunnelingbarrier layer 312. A hard mask layer 316 (e.g., a top electrode oftantalum) is formed on the free layer 314.

In this process, the MTJ stack 300 is subjected to a magnetic annealingprocess in a vacuum. A pattern is then applied to the MTJ stack using alithography technique. A photoresist (not shown in FIG. 3) is formed onthe hard mask layer 316. The patterned cell size may be larger than thefinal size. Each of the aforementioned layers may include one or morelayers or films.

Next, the MTJ stack 300 is etched using an etching process such asreactive ion etching. The etching process includes trimming the size ofthe photoresist, patterning the hard mask layer 316, removing thephotoresist, etching the free layer 314, etching the tunneling barrierlayer 312, etching the first pinned layer 306, the coupling layer 308and the second pinned layer 310, and etching the AFM layer 304. Next, apassivation layer is deposited to protect the MTJ storage element andthe interlayer dielectric (ILD) insulator layer 318. A combination stackmay be specified, along with a low deposition temperature to protect theMTJ and promote adhesion between the MTJ and the ILD. Finally,planarization and metallization is performed.

The MTJ stack 300 is susceptible to damage during the etching processdue to redeposition of etching byproducts. For example, removal ofphotoresist may include processes such as oxygen ashing. Oxygen ashingcan cause damage to the hard mask layer 316 during the photoresistremoval process. Oxygen ashing can also cause damage to upper portions320 of sidewalls of the free layer 314. As described above, the etchingprocess proceeds from etching the hard mask layer 316 at the top of theMTJ stack 300 towards etching the pinned layers at the bottom of thestack. As the etching process progresses deeper down the MTJ stack,damage can be caused to sidewalls 322 of the free layer 314. As theetching process proceeds further down the stack, the upper portions 324and lower portions 326 of the sidewalls of the tunneling barrier layer312 may also be damaged.

Non-volatile byproducts of the etching process may settle asre-deposited films around the sidewalls of MTJ devices. The re-depositedfilms may act as leakage paths along the sidewalls, thereby reducing themagnetic resistance (MR) ratio of the MTJ. Such process related damagesmay result in significantly lower yields. Existing techniques do notprovide an effective solution for protecting MTJs from at least all theprocess related damages described above.

One technique for reducing the detrimental effects of re-deposited filmsis ion beam etching at shallow angles, with multiple steps at differention incident angles. The shallow angle step cleans the sidewallre-deposition. Unfortunately, the use of such directional etchingtechniques becomes increasingly difficult as height to space ratios ofMTJs increase along with MTJ density in current high density of MTJarrays.

A second technique for reducing the detrimental effects of re-depositedfilms is single step etching, which relies on etch optimization toreduce sidewall re-deposition. The etch optimization is sensitive to MTJmaterial, size, and spacing. The final etch profile is generally taperedto reduce sidewall re-deposition. The tapered etch profile may result inreduced density of MTJs in a high density MTJ array.

A third technique for reducing the detrimental effects of re-depositedfilms and the detrimental effects of plasma damage is two-step etching,in which a first step etches down to the tunnel barrier only. Thesidewall of the MTJ is then encapsulated in dielectric material. Througheither a second lithography level or a spacer masking process, an etchmask overlapping the MTJ is formed after the first etching step. Thisetch mask is then used to etch the remaining MTJ stack materials. Thistechnique physically separates the re-deposition material and the plasmafor a second part of the etch from the active magnetic layer and thetunnel barrier region.

An example of a currently known two-step technique for etching an MTJ,which attempts to reduce detrimental effects of re-deposited films andplasma damage, is described with reference to FIGS. 4A and 4B. FIG. 4A,illustrates layers of an MTJ structure 400 after a first etching step.The MTJ structure 400 includes a substrate 402, a bottom electrode layer404, magnetic layers 406, a top electrode 408, a spacer 410 and aconductive hard mask 412. In this example, a first etching step stops onthe magnetic layers 406 of the MTJ and forms the spacer 410 around sidesof the top electrode 408 and the conductive hard mask 412 of the MTJ.

A second etching step stops on the substrate 402 and defines the lateraldimensions of the magnetic layers 406 and the bottom electrode layer 404of the MTJ. Unfortunately, lithographic etching techniques forperforming the second etching step in high-density MTJ arrays aredifficult to implement. Moreover, the use of lithographic etchingtechniques for the second etching step can add an additional mask leveland associated costs to the fabrication process.

A spacer defined etching process using SiNx (silicon nitride) or SiOx(silicon oxide) as the spacer material has been performed in thesemiconductor industry. Unfortunately, SiNx and SiOx are not stronglyresistant to the etchants and processes that are used to etch themagnetic layers 406 and the bottom electrode layer 404 of the MTJ. Thus,as shown in FIG. 4B, a spacer 410 made from SiNx or SiOx issignificantly eroded during a spacer defined second etching step. Theerosion of the spacer 410 results in a tapered etch profile and permitsre-deposition films 414 to come into close proximity with the bottomelectrode layer 404, the magnetic layers 406 and/or the conductive hardmask 412 of the MTJ. Thus, the re-deposition films 414 may stillfacilitate shunting between these layers and detrimentally affect theelectrical resistance characteristics of the MTJ.

A method of implementing a multi-step MTJ etching process, in which thespacer is protected during a second etching step according to an aspectof the present disclosure, is described in FIGS. 5A-5J. FIG. 5Aillustrates layers of an MTJ structure 500 after a first etching stepand deposition of the spacer film according to an aspect of the presentdisclosure. The MTJ structure 500 includes a substrate 502, a firstelectrode layer 504 deposited on the substrate 502 of the MTJ. The MTJstructure 500 also includes a magnetic layer 506 deposited on the firstelectrode layer 504, a second electrode layer 508 deposited on themagnetic layers 506, a first conductive hard mask 512 layer deposited onthe second electrode layer 508 and an first spacer layer 510 depositedover the first conductive hard mask 512.

The first etching step defines the lateral dimensions of the secondelectrode layer 508 and the first conductive hard mask. The first spacerlayer 510 is deposited after the first etching step. The first spacerlayer 510 is deposited on the first conductive hard mask 512, on thesecond electrode layer 508, and on the magnetic layers 506 of the MTJ.In one configuration, a first portion 520 of the first spacer layer 510,which abuts sidewalls of the first conductive hard mask 512, is thinnerthan a second portion 522 of the first spacer layer 510, which abuts atop surface of the first conductive hard mask 512. This can be achievedby reducing the level of conformality during deposition of the firstspacer layer 510, for example, by changing the chamber pressure or thebias power. The first spacer layer 510 may be SiNx. The thickness of thefirst portion 520 of the first spacer layer 510 may be about 10-50nanometers and the thickness of the second portion 522 of the firstspacer layer 510 may be greater than 50 nanometers. The greaterthickness of second portion 522 of the first spacer layer 510 mayprovide increased process margins for subsequent planarizationprocesses, for example.

FIG. 5B shows a schematic cross-sectional view further illustrating theMTJ structure 500 during fabrication according to an aspect of thepresent disclosure. In this configuration, a first dielectric layer 514is deposited on the first spacer layer 510. In this example, firstdielectric layer 514 is deposited on the first spacer layer 510 afterthe first spacer layer 510 is conformally deposited on the firstconductive hard mask 512, on the second electrode layer 508 and on themagnetic layers 506 of the MTJ.

FIG. 5C shows a schematic cross-sectional view further illustrating theMTJ structure 500 during fabrication according to an aspect of thepresent disclosure. In this configuration, the first dielectric layer514 is planarized using well known methods such as a chemical mechanicalplanarization process. Planarization of the first dielectric layer 514stops on the first spacer layer 510 and forms a surface of the firstdielectric layer 514 that is substantially co-planar with the surface ofthe second portion 522 of the first spacer layer 510.

A planarization process that stops on a nitride layer, such as the firstspacer layer 510, while reducing or even minimizing oxide dishing mayinclude the use of a selective slurries, reduced forces and/or higherspeeds to improve planarization performance. Examples of techniques forimproving planarization performance that may be applied to the step ofplanarizing the first dielectric layer 514 to stop at the first spacerlayer 510 according to aspects of the present disclosure are describedin Withers et al., “Wide margin CMP for STI”, Solid State Technology,0038111X, Jul 98, Vol. 41, Issue 7, the disclosure of which is expresslyincorporated by reference herein in its entirety.

In FIG. 5D, the second portion 522 of the first spacer layer 510 isselectively removed. This step can be performed using currently knownprocesses such as the highly selective etching of SiNx in well-knowngate spacer processes, for example. Examples of highly selective etchingof SiNx are described in Sunghoon Lee et al., JVacSciTEch B 20(1),P131-7, 2010. A recess 516 in the first dielectric layer 514 is formedby removal of the second portion 522 of the first spacer layer 510. Therecess 516 is aligned with the outside vertical surface of the firstportion 520 of the first spacer layer 510, and overlaps the firstconductive hard mask 512 and the second electrode layer 508.

In this aspect of the present disclosure, the material of the firstdielectric layer 514 is selected for having properties that allow theselective removal of the first spacer layer 510 material to form therecess 516 within the first dielectric layer 514. In one example, thematerial of the first dielectric layer 514 is SiOx.

FIG. 5E further illustrates the MTJ structure 500 during fabricationaccording to an aspect of the present disclosure. In this configuration,the recess 516 is filled with a second conductive hard mask 518. Fillingof the recess 516 with the second conductive hard mask 518 may beperformed after removal of the second portion 522 of the first spacerlayer 510. The second conductive hard mask may be, for example,tantalum, hafnium, or platinum. The material selection is based on theetching chemistry to be used. The material can be treated so that it isfurther resistant to the etching chemicals. A common planarizationprocesses, such as chemical mechanical polishing (CMP), removes excessmaterials outside of the recess 516, such that the resulting secondconductive hard mask 518 is also aligned with the outside extent of thefirst portion 520 of the first spacer layer 510.

In FIG. 5F, the first dielectric layer 514 is removed after the recess516 is filled with a second conductive hard mask 518. The firstdielectric layer 514 may be removed by plasma etching, for example. Inthis configuration, removal of the first dielectric layer 514 leaves thesecond conductive hard mask 518 aligned with the first portion 520 ofthe first spacer layer 510, and overlapping the first conductive hardmask 512 and the second electrode layer 508. At this stage, remainingportions of the first spacer layer 510 include the first portion 520that abuts sidewalls of the first conductive hard mask and the secondelectrode layer 508. Other portions of the first spacer layer 510include the third portions 524 that abut the magnetic layers 506 of theMTJ where the magnetic layers 506 are not overlapped by the secondconductive hard mask 518.

In FIG. 5G, the third portions 524 of the first spacer layer 510 areremoved after the first dielectric layer 514 is removed with ananisotropic etch. In one example, the first dielectric layer is a SiNxmaterial. The third portions 524 of the first spacer layer 510 may beremoved by plasma etching of the SiNx material. The second conductivehard mask 518 may prevent the second portion 522 of the first spacerlayer 510 from being removed during this step.

In FIG. 5H, the magnetic layers 506 of the MTJ are etched during asecond etching step after the third portions 524 of the first dielectriclayer 514 are removed. This step may be performed by reactive ionetching, or ion beam etching, for example. The magnetic layers 506 ofthe MTJ are masked by the second conductive hard mask 518 during thisetching step so the lateral dimensions of the magnetic layers 506 aresubstantially aligned with the lateral dimensions of the secondconductive hard mask 518. Thus, the magnetic layers 506 of the MTJ areetched in a pattern defined by the second conductive hard mask 518.According to an aspect of the present disclosure, the top surface of thesecond conductive hard mask 518 may be modified to enhance etchresistance to this second etching step.

In FIGURE SI, a second spacer layer 526 is conformally deposited overthe second conductive hard mask 518, the second portions 522 of thefirst spacer layer 510, the magnetic layer 506 and the first electrodelayer 504. The second spacer layer 526 may be conformally depositedafter the magnetic layers 506 of the MTJ are etched. The second spacerlayer 526 may be a SiNx material, for example. The second spacer layer526 and the second portion of the first spacer layer 510 protect thesecond electrode layer 508, the magnetic layers 506 and the firstelectrode layer 504 from re-deposition films, oxidation, toolcontamination, etc.

FIG. 5J shows a schematic cross-sectional view illustrating the MTJstructure 500 after fabrication according to an aspect of the presentdisclosure. In this configuration, a second dielectric layer 528 isdeposited over the second spacer layer after the second spacer layer isconformally deposited. The second dielectric layer 528 may be a SiOxmaterial, for example. The second dielectric layer 528 may then beplanarized using a conventional chemical mechanical planarizationprocess. A conductive interconnect 530 may be formed in the seconddielectric layer 528 and coupled to the second conductive hard mask 518to provide a conductive path to the first conductive hard mask 512 andthe second electrode layer 508. The conductive interconnect may be aconventionally formed Cu interconnect, for example.

FIG. 6 is a process flow diagram illustrating a method of fabricating amagnetic tunnel junction (MTJ) apparatus according to an aspect of thepresent disclosure. It should be noted that the following descriptiondoes not necessarily reflect the actual sequence of film growth. Themethod 600 includes conformally depositing a first spacer layer on afirst conductive hard mask, on a top electrode, and on magnetic layersof the MTJ at block 602. A first portion of the first spacer layer isdeposited on sidewalls of the first conductive hard mask and a secondportion of the spacer layer is deposited on a top surface of the firstconductive hard mask. At block 604, the method includes depositing afirst dielectric layer over the first spacer layer. At block 606, themethod includes planarizing the first dielectric layer down to thesecond portion of first spacer layer. At block 608, the second portionof the spacer layer is selectively removed to form a recess within thefirst dielectric layer. According to an aspect of the disclosure, therecess is aligned with the first portion of the first spacer layer. Atblock 610, the recess is filled with a conductive material to form asecond conductive hard mask on the first portion of the first spacerlayer and on the first conductive hard mask.

An MTJ apparatus according to another aspect of the present disclosureincludes a first means for masking a top electrode that is coupled to astack of MTJ layers and for providing a conductive path to the topelectrode. The first means for masking the top electrode and providing aconductive hard mask may include the first conductive hard mask 512 thatis described above with respect to FIGS. 5A-5J, for example. Accordingto this aspect of the disclosure, the apparatus also includes a meansfor protecting sidewalls of the first means. The protecting means mayinclude the first spacer layer 510 that is described in FIGS. 5A-5J, forexample. According to this aspect of the disclosure, the apparatus alsoincludes second means for masking the stack of MTJ magnetic layers andfor electrically coupling to the first conductive path. The second meansfor masking the stack of MTJ magnetic layers and for electricallycoupling to the first conductive path may include the second conductivehard mask 518 that is in FIGS. 5E-5J, for example.

In another configuration, the aforementioned means may be any materialor any layer configured to perform the functions recited by theaforementioned means. Although specific means have been set forth, itwill be appreciated by those skilled in the art that not all of thedisclosed means are required to practice the disclosed configurations.Moreover, certain well known means have not been described, to maintainfocus on the disclosure.

FIG. 7 is a block diagram showing an exemplary wireless communicationsystem 700 in which an aspect of the disclosure may be advantageouslyemployed. For purposes of illustration, FIG. 7 shows three remote units720, 730, and 750 and two base stations 740. It will be recognized thatwireless communication systems may have many more remote units and basestations. Remote units 720, 730, and 750 include IC devices 725A, 725Cand 725B that include the disclosed MTJ apparatus. It will be recognizedthat other devices may also include the disclosed MTJ apparatus, such asthe base stations, switching devices, and network equipment. FIG. 7shows forward link signals 780 from the base station 740 to the remoteunits 720, 730, and 750 and reverse link signals 790 from the remoteunits 720, 730, and 750 to base stations 740.

In FIG. 7, remote unit 720 is shown as a mobile telephone, remote unit730 is shown as a portable computer, and remote unit 750 is shown as afixed location remote unit in a wireless local loop system. For example,the remote units may be mobile phones, hand-held personal communicationsystems (PCS) units, portable data units such as personal dataassistants, GPS enabled devices, navigation devices, set top boxes,music players, video players, entertainment units, fixed location dataunits such as meter reading equipment, or other devices that store orretrieve data or computer instructions, or combinations thereof.Although FIG. 7 illustrates remote units according to the teachings ofthe disclosure, the disclosure is not limited to these exemplaryillustrated units. Aspects of the disclosure may be suitably employed inmany devices, which include MTJ apparatus.

FIG. 8 is a block diagram illustrating a design workstation used forcircuit, layout, and logic design of a semiconductor component, such asthe MTJ apparatus disclosed above. A design workstation 800 includes ahard disk 801 containing operating system software, support files, anddesign software such as Cadence or OrCAD. The design workstation 800also includes a display 802 to facilitate design of a circuit 810 or asemiconductor component 812 such as an MTJ apparatus. A storage medium804 is provided for tangibly storing the circuit design 810 or thesemiconductor component 812. The circuit design 810 or the semiconductorcomponent 812 may be stored on the storage medium 804 in a file formatsuch as GDSII or GERBER. The storage medium 804 may be a CD-ROM, DVD,hard disk, flash memory, or other appropriate device. Furthermore, thedesign workstation 800 includes a drive apparatus 803 for acceptinginput from or writing output to the storage medium 804.

Data recorded on the storage medium 804 may include specify logiccircuit configurations, pattern data for photolithography masks, or maskpattern data for serial write tools such as electron beam lithography.The data may further include logic verification data such as timingdiagrams or net circuits associated with logic simulations. Providingdata on the storage medium 804 facilitates the design of the circuitdesign 810 or the semiconductor component 812 by decreasing the numberof processes for designing semiconductor wafers.

For a firmware and/or software implementation, the methodologies may beimplemented with modules (e.g., procedures, functions, and so on) thatperform the functions described herein. A machine-readable mediumtangibly embodying instructions may be used in implementing themethodologies described herein. For example, software codes may bestored in a memory and executed by a processor unit. Memory may beimplemented within the processor unit or external to the processor unit.As used herein, the term “memory” refers to types of long term, shortterm, volatile, nonvolatile, or other memory and is not to be limited toa particular type of memory or number of memories, or type of media uponwhich memory is stored.

If implemented in firmware and/or software, the functions may be storedas one or more instructions or code on a computer-readable medium.Examples include computer-readable media encoded with a data structureand computer-readable media encoded with a computer program.Computer-readable media includes physical computer storage media. Astorage medium may be an available medium that can be accessed by acomputer. By way of example, and not limitation, such computer-readablemedia can include RAM, ROM, EEPROM, CD-ROM or other optical diskstorage, magnetic disk storage or other magnetic storage devices, orother medium that can be used to store desired program code in the formof instructions or data structures and that can be accessed by acomputer; disk and disc, as used herein, includes compact disc (CD),laser disc, optical disc, digital versatile disc (DVD), floppy disk andBlu-ray disc where disks usually reproduce data magnetically, whilediscs reproduce data optically with lasers. Combinations of the aboveshould also be included within the scope of computer-readable media.

In addition to storage on computer readable medium, instructions and/ordata may be provided as signals on transmission media included in acommunication apparatus. For example, a communication apparatus mayinclude a transceiver having signals indicative of instructions anddata. The instructions and data are configured to cause one or moreprocessors to implement the functions outlined in the claims.

The exemplary aspects discussed herein, beneficially allow the MTJ stackto be protected from at least the process related damages describedabove, thereby generating high yield in the fabrication of MTJs. Itshould be appreciated that the various layers of the MTJ stack areprovided merely for illustration and not for limitation. Additionallayers may be added and/or layers may be removed or combined and maycomprise different materials then illustrated.

It should be appreciated that memory devices including the MTJ storageelements described herein may be included within a mobile phone,portable computer, hand-held personal communication system (PCS) unit,portable data units such as personal data assistants (PDAs), GPS enableddevices, navigation devices, set top boxes, music players, videoplayers, entertainment units, fixed location data units such as meterreading equipment, or any other device that stores or retrieves data orcomputer instructions, or any combination thereof. Accordingly, aspectsof the disclosure may be suitably employed in any device, which includesactive integrated circuitry including memory having MTJ storage elementsas disclosed herein.

Further, it should be appreciated that various to memory devices caninclude an array of MTJ storage elements as disclosed herein.Additionally, the MTJ storage elements disclosed herein may be used invarious other applications, such as in logic circuits. Accordingly,although potions of the foregoing disclosure discuss the stand alone MTJstorage element, it will be appreciated that various aspects can includedevices into which the MTJ storage element is integrated.

Accordingly, aspects can include machine-readable media orcomputer-readable media embodying instructions which when executed by aprocessor transform the processor and any other cooperating elementsinto a machine for performing the functionalities described herein asprovided for by the instructions.

While the foregoing disclosure shows illustrative aspects, it should benoted that various changes and modifications could be made hereinwithout departing from the scope of the disclosure as defined by theappended claims. The functions, steps and/or actions of the methodclaims in accordance with the aspects described herein need not beperformed in any particular order. Furthermore, although elements of theaspects may be described or claimed in the singular, the plural iscontemplated unless limitation to the singular is explicitly stated.

Although the present disclosure and its advantages have been describedin detail, it should be understood that various changes, substitutionsand alterations can be made herein without departing from the technologyof the disclosure as defined by the appended claims. For example,relational terms, such as “above,” “below,” “top” and “bottom” are usedwith respect to a substrate or electronic device. Of course, if thesubstrate or electronic device is inverted, above becomes below, topbecomes bottom and vice versa. Additionally, if oriented sideways, theterms “above,” “below,” “top” and “bottom” may refer to sides of asubstrate or electronic device, for example.

The word “exemplary” is used herein to mean “serving as an example,instance, or illustration.” Any aspect described herein as “exemplary”is not necessarily to be construed as preferred or advantageous overother aspects. Likewise, the term “aspects of the disclosure” does notrequire that all aspects of the disclosure include the discussedfeature, advantage or mode of operation. The terminology used herein isfor the purpose of describing particular aspects only and is notintended to be limiting of aspects of the disclosure.

As used herein, the singular forms “a,” “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises,”“comprising,” “includes” and/or “including,” when used herein, specifythe presence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof

Moreover, the scope of the present application is not intended to belimited to the particular configurations of the process, machine,manufacture, composition of matter, means, methods and steps describedin the specification. As one of ordinary skill in the art will readilyappreciate from the disclosure, processes, machines, manufacture,compositions of matter, means, methods, or steps, presently existing orlater to be developed that perform substantially the same function orachieve substantially the same result as the correspondingconfigurations described herein may be utilized according to the presentdisclosure. Accordingly, the appended claims are intended to includewithin their scope such processes, machines, manufacture, compositionsof matter, means, methods, or steps.

What is claimed is:
 1. A method of fabricating a magnetic tunneljunction (MTJ) apparatus, comprising: conformally depositing a firstspacer layer on a first conductive hard mask, on a first electrodelayer, and on magnetic layers of the MTJ, a first portion of the firstspacer layer being deposited on sidewalls of the first conductive hardmask and a second portion of the spacer layer being deposited on asurface of the first conductive hard mask; selectively removing thesecond portion of the first spacer layer to create a recess within adielectric layer, the recess being aligned with the first portion of thefirst spacer layer; and filling the recess with a conductive material toform a second conductive hard mask on the first portion of the firstspacer layer and on the first conductive hard mask.
 2. The method ofclaim 1, comprising depositing the first portion of the first spacerlayer with a thickness less than the second portion of the first spacerlayer.
 3. The method of claim 1, further comprising etching the magneticlayers of the MTJ in a pattern defined by the second conductive hardmask.
 4. The method of claim 1, further comprising depositing a firstdielectric layer on the first spacer layer.
 5. The method of claim 4,further comprising planarizing the first dielectric layer to expose thesecond portion of first spacer layer.
 6. The method of claim 5, furthercomprising removing remaining portions of the first dielectric layerafter filling the recess with the conductive material.
 7. The method ofclaim 6, further comprising removing third portions of the first spacerlayer, the third portions of the first spacer layer abutting themagnetic layers of the MTJ where the magnetic layers are not overlappedby the second conductive hard mask.
 8. The method of claim 7, furthercomprising etching the magnetic layers of the MTJ in a pattern definedby the second conductive hard mask after removing the third portions ofthe first spacer layer.
 9. The method of claim 1, further comprisingconformally depositing a second spacer layer over the second conductivehard mask, the second portion of the first spacer layer, the magneticlayers and the a second electrode layer.
 10. The method of claim 9,further comprising: depositing a second dielectric layer over the secondspacer layer; planarizing the second dielectric layer; and forming aconductive interconnect in the second dielectric layer, the conductiveinterconnect forming a conductive path to the second conductive hardmask.
 11. The method of claim 1, further comprising integrating the MTJapparatus into a mobile phone, a set top box, a music player, a videoplayer, an entertainment unit, a navigation device, a computer, ahand-held personal communication systems (PCS) unit, a portable dataunit, and/or a fixed location data unit.
 12. A method of fabricating amagnetic tunnel junction (MTJ) apparatus, comprising steps for:conformally depositing a first spacer layer on a first conductive hardmask, on a first electrode layer, and on magnetic layers of the MTJ, afirst portion of the first spacer layer being deposited on sidewalls ofthe first conductive hard mask and a second portion of the spacer layerbeing deposited on a surface of the first conductive hard mask;selectively removing the second portion of the first spacer layer tocreate a recess within a dielectric layer, the recess being aligned withthe first portion of the first spacer layer; and filling the recess witha conductive material to form a second conductive hard mask on the firstportion of the first spacer layer and on the first conductive hard mask.13. The method of claim 12, further comprising steps for integrating theMTJ apparatus into a mobile phone, a set top box, a music player, avideo player, an entertainment unit, a navigation device, a computer, ahand-held personal communication systems (PCS) unit, a portable dataunit, and/or a fixed location data unit.